761 lines
18 KiB
Plaintext
761 lines
18 KiB
Plaintext
#include <core.p4>
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#include <tna.p4>
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#define ETHERTYPE_IPV4 0x0800
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#define ETHERTYPE_ROCE 0x8915
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#define IPv4_PROTO_TCP 0x06
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#define IPv4_PROTO_UDP 0x11
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#define CMS_RDMA_PAYLOAD_SIZE 8
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#ifndef MAX_SUPPORTED_QPS
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#define MAX_SUPPORTED_QPS 256 // Maximum number of supported QPs. Specifies table and register sizes
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// #define MAX_SUPPORTED_QPS 65536 // Used when benchmarking tons of QPs
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#endif
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typedef bit<32> ipv4_address_t;
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typedef bit<32> iCRC_t;
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typedef bit<32> remote_key_t;
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typedef bit<24> queue_pair_t;
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typedef bit<24> psn_t; // RoCEv2 中的数据包序列号 (Packet sequence number)
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typedef bit<16> qp_reg_index_t; // 用于为每个 QP 存放其 PSN. 该字段是充当那个寄存器的索引号
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typedef bit<32> slot_nums_t;
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typedef bit<32> memory_slot_t; // 内存插槽(空隙). 由 Key-Write 和 Append 原语所共享, 出于某些原因, 它们都被限制在最大 32 bits
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typedef bit<64> memory_address_t; // 物理内存地址(共 2^64)
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// 定义不同的数据包类型 (Normal 和 Mirror), 用于桥接报头中
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typedef bit<8> pkt_type_t;
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const pkt_type_t PKT_TYPE_NORMAL = 1;
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const pkt_type_t PKT_TYPE_MIRROR = 2;
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// 定义不同的镜像数据包类型 (I2E 和 E2E)
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typedef bit<3> mirror_type_t;
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const mirror_type_t MIRROR_TYPE_I2E = 1;
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const mirror_type_t MIRROR_TYPE_E2E = 2;
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// 14 Bytes
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header ethernet_h{
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bit<48> dstAddr;
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bit<48> srcAddr;
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bit<16> etherType;
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}
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// 20 Bytes
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header ipv4_h{
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bit<4> version;
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bit<4> ihl;
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bit<6> dscp;
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bit<2> ecn;
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bit<16> totalLen;
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bit<16> identification;
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bit<3> flags;
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bit<13> fragOffset;
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bit<8> ttl;
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bit<8> protocol;
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bit<16> hdrChecksum;
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ipv4_address_t srcAddr;
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ipv4_address_t dstAddr;
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}
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// 20 Bytes
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header tcp_h {
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bit<16> srcPort;
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bit<16> dstPort;
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bit<32> seq_no;
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bit<32> ack_no;
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bit<4> data_offset;
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bit<4> res;
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bit<8> flags;
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bit<16> window;
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bit<16> checksum;
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bit<16> urgent_ptr;
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}
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// 8 Bytes
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header udp_h{
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bit<16> srcPort;
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bit<16> dstPort;
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bit<16> totalLen;
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bit<16> checksum;
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}
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// Global Route Header (GRH) (40 Bytes)
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header infiniband_grh_h{
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bit<4> version;
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bit<8> class;
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bit<20> flow_lab;
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bit<16> pay_len;
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bit<8> next_hdr;
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bit<8> hop_lim;
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bit<128> src_gid;
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bit<128> dst_gid;
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}
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// Base Transport Header (BTH) (12 Bytes)
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header infiniband_bth_h{
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bit<8> opcode;
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bit<1> solicitedEvent;
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bit<1> migReq;
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bit<2> padCount;
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bit<4> transportHeaderVersion;
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bit<16> partitionKey;
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bit<1> fRes;
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bit<1> bRes;
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bit<6> reserved1;
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bit<24> destinationQP;
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bit<1> ackRequest;
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bit<7> reserved2;
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psn_t packetSequenceNumber;
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}
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// Atomic Extended Transport Header (ATOMIC_ETH) (28 bytes)
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header infiniband_atomiceth_h{
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memory_address_t virtualAddress;
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bit<32> rKey;
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bit<64> data;
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bit<64> compare;
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}
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// iCRC 字段 (4 Bytes)
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header infiniband_icrc_h{
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bit<32> iCRC;
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}
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header mirror_h{
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pkt_type_t pkt_type;
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}
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header mirror_bridged_metadata_h{
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pkt_type_t pkt_type;
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}
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struct headers{
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mirror_bridged_metadata_h bridged_md;
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/* Normal Header */
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ethernet_h ethernet;
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ipv4_h ipv4;
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udp_h udp;
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tcp_h tcp;
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/* RoCEv2 Header */
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infiniband_grh_h grh;
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infiniband_bth_h bth;
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infiniband_atomiceth_h atomic_eth;
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infiniband_icrc_h icrc;
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}
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struct ingress_metadata_t{
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pkt_type_t pkt_type;
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MirrorId_t mirror_session;
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}
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struct egress_metadata_t{
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/* Store Flowkey */
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ipv4_address_t srcIP;
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ipv4_address_t dstIP;
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bit<16> srcPort;
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bit<16> dstPort;
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bit<8> proto;
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/* RDMA Metadata */
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psn_t rdma_psn;
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remote_key_t remote_key;
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queue_pair_t queue_pair;
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/* Used to locate where to store in the rdma memory */
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memory_address_t memory_address_start;
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memory_address_t memory_address_offset;
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/* Slot is used as an intermediary for calculating rdma memory address */
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memory_slot_t colletcor_dst_slot;
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memory_slot_t rank_num_slots;
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memory_slot_t rank_slot_offset;
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memory_slot_t rank_start_slot;
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qp_reg_index_t qp_reg_index;
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bit<8> multicast_pkt_num;
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}
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/* 入口解析器部分校对完毕, 没有问题 */
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parser TofinoIngressParser(packet_in pkt,
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/* User */
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inout ingress_metadata_t ig_md,
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/* Intrinsic */
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out ingress_intrinsic_metadata_t ig_intr_md)
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{
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state start{
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pkt.extract(ig_intr_md);
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transition select(ig_intr_md.resubmit_flag){
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1 : parse_resubmit;
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0 : parse_port_metadata;
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}
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}
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state parse_resubmit{
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transition reject;
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}
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state parse_port_metadata{
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pkt.advance(64); // Tofino 1
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transition accept;
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}
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}
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parser SwitchIngressParser(packet_in pkt,
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/* User */
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out headers hdr,
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out ingress_metadata_t ig_md,
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/* Intrinsic */
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out ingress_intrinsic_metadata_t ig_intr_md)
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{
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TofinoIngressParser() tofino_parser;
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state start{
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tofino_parser.apply(pkt, ig_md, ig_intr_md);
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transition parse_ethernet;
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}
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state parse_ethernet{
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pkt.extract(hdr.ethernet);
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transition select(hdr.ethernet.etherType){
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ETHERTYPE_IPV4: parse_ipv4;
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ETHERTYPE_ROCE: parse_grh;
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default: accept;
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}
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}
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state parse_ipv4{
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pkt.extract(hdr.ipv4);
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transition select(hdr.ipv4.protocol){
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IPv4_PROTO_UDP: parse_udp;
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IPv4_PROTO_TCP: parse_tcp;
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default: accept;
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}
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}
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state parse_tcp{
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pkt.extract(hdr.tcp);
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transition accept;
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}
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state parse_udp{
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pkt.extract(hdr.udp);
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transition accept;
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}
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state parse_grh{
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pkt.extract(hdr.grh);
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transition accept;
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}
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}
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/* 入口控制块部分校对完毕, 没有问题 */
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control SwitchIngress(inout headers hdr,
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/* User */
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inout ingress_metadata_t ig_md,
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/* Intrinsic */
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in ingress_intrinsic_metadata_t ig_intr_md,
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in ingress_intrinsic_metadata_from_parser_t ig_intr_prsr_md,
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inout ingress_intrinsic_metadata_for_deparser_t ig_intr_dprsr_md,
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inout ingress_intrinsic_metadata_for_tm_t ig_intr_tm_md)
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{
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/* 根据目的以太网地址来设置多播组 ID, 从而对数据包执行多播操作 */
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action prep_multiwrite(bit<16> mcast_grp)
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{
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ig_intr_tm_md.mcast_grp_a = mcast_grp;
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}
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table tbl_prep_multicast
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{
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key = {
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hdr.ethernet.dstAddr: exact;
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}
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actions = {
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prep_multiwrite;
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@defaultonly NoAction;
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}
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default_action = NoAction;
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size = 1024;
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}
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/* 根据目的以太网地址决定数据包执行转发到对应的目的端口, 或者是丢弃该数据包 */
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action forward(PortId_t port)
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{
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ig_intr_tm_md.ucast_egress_port = port;
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}
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action to_cpu()
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{
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ig_intr_tm_md.ucast_egress_port = 66;
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}
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action drop()
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{
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ig_intr_dprsr_md.drop_ctl = 1;
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}
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table tbl_forward
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{
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key = {
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hdr.ethernet.dstAddr: exact;
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}
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actions = {
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forward;
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to_cpu;
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drop;
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}
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default_action = to_cpu;
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size = 1024;
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}
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apply
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{
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tbl_forward.apply();
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tbl_prep_multicast.apply();
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// 为 Egress Control 准备桥接元数据
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hdr.bridged_md.setValid();
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hdr.bridged_md.pkt_type = PKT_TYPE_NORMAL;
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}
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}
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/* 入口逆解析器部分校对完毕, 没有问题 */
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control SwitchIngressDeparser(packet_out pkt,
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inout headers hdr,
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in ingress_metadata_t ig_md,
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in ingress_intrinsic_metadata_for_deparser_t ig_intr_dprsr_md)
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{
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Mirror() mirror;
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apply{
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// 如果时 Ingress-to-Egress 镜像操作
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if (ig_intr_dprsr_md.mirror_type == MIRROR_TYPE_I2E){
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// Emit Mirror，并附加上 mirror_h 报头
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mirror.emit<mirror_h>(ig_md.mirror_session, {ig_md.pkt_type});
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}
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pkt.emit(hdr);
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}
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}
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/* 出口解析器部分校对完毕, 没有问题 */
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parser SwitchEgressParser(packet_in pkt,
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/* User */
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out headers hdr,
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out egress_metadata_t eg_md,
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/* Intrinsic */
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out egress_intrinsic_metadata_t eg_intr_md)
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{
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state start{
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pkt.extract(eg_intr_md);
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transition parse_metadata;
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}
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state parse_metadata{
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mirror_h mirror_md = pkt.lookahead<mirror_h>();
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// 根据镜像元数据中的 pkt_type 字段决定下一步要执行的解析状态
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transition select(mirror_md.pkt_type){
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PKT_TYPE_MIRROR: parse_mirror_md;
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PKT_TYPE_NORMAL: parse_bridged_md;
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default: accept;
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}
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}
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// 提取桥接元数据
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state parse_bridged_md{
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pkt.extract(hdr.bridged_md);
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transition parse_ethernet;
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}
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// 如果是镜像数据包, 在本方案中表示是遥测报告数据包, 提取其镜像元数据
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state parse_mirror_md{
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mirror_h mirror_md;
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pkt.extract(mirror_md);
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transition parse_ethernet;
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}
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state parse_ethernet{
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pkt.extract(hdr.ethernet);
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transition select(hdr.ethernet.etherType){
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ETHERTYPE_IPV4: parse_ipv4;
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ETHERTYPE_ROCE: parse_grh;
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default: accept;
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}
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}
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state parse_ipv4{
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pkt.extract(hdr.ipv4);
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transition select(hdr.ipv4.protocol){
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IPv4_PROTO_UDP: parse_udp;
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IPv4_PROTO_TCP: parse_tcp;
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default: accept;
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}
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}
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state parse_udp{
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pkt.extract(hdr.udp);
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transition accept;
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}
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state parse_tcp{
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pkt.extract(hdr.tcp);
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transition accept;
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}
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state parse_grh{
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pkt.extract(hdr.grh);
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transition accept;
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}
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}
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/* 准备 KeyWrite 控制块部分校对完毕, 没有问题 */
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control ControlPrepareMemoryAddress(inout headers hdr,
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inout egress_metadata_t eg_md,
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in egress_intrinsic_metadata_t eg_intr_md)
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{
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Hash<slot_nums_t>(HashAlgorithm_t.CRC32) hash_slot;
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// 用于区分多播中产生的多个数据包 (因为每来一个数据包都要递增寄存器中的值, 并且还是循环)
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Register<bit<8>, bit<1>>(MAX_SUPPORTED_QPS) reg_multicast_iterator;
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RegisterAction<bit<8>, bit<1>, bit<8>>(reg_multicast_iterator) get_pkt_number = {
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void apply(inout bit<8> stored, out bit<8> output)
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{
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// 首先将内部存储的 stored 输出给 output
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output = stored;
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// 如果当前存储的值大于 hash_nums - 1, 则需要将 stored 置 0
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if(stored >= 3){
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stored = 0;
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}
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// 否则, 对 stored 进行递增
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else{
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stored = stored + 1;
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}
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}
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};
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// 根据当前数据包的多播 ID 号, 来获得其在 CMS 中存储的起始插槽位置
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action get_start_slot(memory_slot_t start_slot)
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{
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// 获取起始插槽位置 (CMS 中每行的开头)
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eg_md.rank_start_slot = start_slot;
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}
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table tbl_get_start_slot{
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key = {
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eg_md.multicast_pkt_num: exact;
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}
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actions = {
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get_start_slot;
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NoAction;
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}
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size = 8;
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default_action = NoAction();
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}
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// 根据目的 IPv4 地址, 获取 Collector 的 RDMA 元数据信息
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action set_server_info(remote_key_t remote_key, queue_pair_t queue_pair, memory_address_t memory_address_start, memory_slot_t rank_num_slots, qp_reg_index_t qp_reg_index)
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{
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eg_md.remote_key = remote_key;
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eg_md.queue_pair = queue_pair;
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eg_md.memory_address_start = memory_address_start;
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eg_md.rank_num_slots = rank_num_slots;
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eg_md.qp_reg_index = qp_reg_index;
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}
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table tbl_getRDMAMetadata
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{
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key = {
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hdr.ethernet.dstAddr: exact;
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}
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actions = {
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set_server_info;
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}
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// 单个 Translator 不可能负责比这更多的工作
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size = MAX_SUPPORTED_QPS;
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}
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// 通过哈希函数计算出插槽的偏移量 (计算结果为 bit<32> 类型)
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action cal_slot_offset()
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{
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eg_md.rank_slot_offset = hash_slot.get({eg_md.srcIP,
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eg_md.dstIP,
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eg_md.srcPort,
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eg_md.dstPort,
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eg_md.proto,
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eg_md.multicast_pkt_num});
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}
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table tbl_cal_slot_offset
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{
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key = {}
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actions = {
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cal_slot_offset;
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}
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size = 1;
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default_action = cal_slot_offset();
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}
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// 将这个偏移量与实际可用的插槽数量进行绑定 (通过与 mask 进行按位与运算)
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action bound_memory_slot(memory_slot_t mask)
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{
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eg_md.rank_slot_offset = eg_md.rank_slot_offset & mask;
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}
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table tbl_bound_memory_slot
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{
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key = {
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eg_md.rank_num_slots: exact;
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}
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actions = {
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bound_memory_slot;
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}
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const entries = {
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2: bound_memory_slot(0x00000001);
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4: bound_memory_slot(0x00000003);
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8: bound_memory_slot(0x00000007);
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16: bound_memory_slot(0x0000000f);
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32: bound_memory_slot(0x0000001f);
|
||
64: bound_memory_slot(0x0000003f);
|
||
128: bound_memory_slot(0x0000007f);
|
||
256: bound_memory_slot(0x000000ff);
|
||
512: bound_memory_slot(0x000001ff);
|
||
1024: bound_memory_slot(0x000003ff);
|
||
2048: bound_memory_slot(0x000007ff);
|
||
4096: bound_memory_slot(0x00000fff);
|
||
8192: bound_memory_slot(0x00001fff);
|
||
16384: bound_memory_slot(0x00003fff);
|
||
32768: bound_memory_slot(0x00007fff);
|
||
65536: bound_memory_slot(0x0000ffff);
|
||
131072: bound_memory_slot(0x0001ffff);
|
||
262144: bound_memory_slot(0x0003ffff);
|
||
524288: bound_memory_slot(0x0007ffff);
|
||
1048576: bound_memory_slot(0x000fffff);
|
||
2097152: bound_memory_slot(0x001fffff);
|
||
4194304: bound_memory_slot(0x003fffff);
|
||
8388608: bound_memory_slot(0x007fffff);
|
||
16777216: bound_memory_slot(0x00ffffff);
|
||
33554432: bound_memory_slot(0x01ffffff);
|
||
67108864: bound_memory_slot(0x03ffffff);
|
||
134217728: bound_memory_slot(0x07ffffff);
|
||
268435456: bound_memory_slot(0x0fffffff);
|
||
536870912: bound_memory_slot(0x1fffffff);
|
||
1073741824: bound_memory_slot(0x3fffffff);
|
||
2147483648: bound_memory_slot(0x7fffffff);
|
||
//4294967296: bound_memory_slot(0xffffffff); //does not fit in 32-bit
|
||
}
|
||
size=64;
|
||
}
|
||
|
||
apply
|
||
{
|
||
// 获取当前数据包的多播 ID 号
|
||
eg_md.multicast_pkt_num = get_pkt_number.execute(0);
|
||
|
||
// 获取 RDMA 元数据信息
|
||
tbl_getRDMAMetadata.apply();
|
||
@stage(1)
|
||
{
|
||
// 计算起始插槽位置和插槽偏移量, 然后联合起来计算出目标插槽位置
|
||
tbl_get_start_slot.apply();
|
||
tbl_cal_slot_offset.apply();
|
||
tbl_bound_memory_slot.apply();
|
||
eg_md.colletcor_dst_slot = eg_md.rank_start_slot + eg_md.rank_slot_offset;
|
||
|
||
// 将内存插槽转换为在物理内存地址中的偏移量
|
||
// 即需要乘以有效载荷的字节数 (此处为 8，即向左位移 3)
|
||
eg_md.memory_address_offset = (memory_address_t)(eg_md.colletcor_dst_slot);
|
||
eg_md.memory_address_offset = eg_md.memory_address_offset * CMS_RDMA_PAYLOAD_SIZE;
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
/* 生成 RDMA 数据包控制块部分校对完毕, 没有问题 */
|
||
control ControlConvertToRDMA(inout headers hdr,
|
||
inout egress_metadata_t eg_md)
|
||
{
|
||
// 分配 32 位的寄存器数组来保存 24 位的 PSN
|
||
Register<bit<32>, qp_reg_index_t>(MAX_SUPPORTED_QPS) reg_rdma_sequence_number;
|
||
RegisterAction<psn_t, qp_reg_index_t, psn_t>(reg_rdma_sequence_number) get_psn = {
|
||
void apply(inout psn_t stored_psn, out psn_t output)
|
||
{
|
||
// 首先输出尚未递增的 PSN
|
||
output = stored_psn;
|
||
// 然后对 PSN 进行递增并覆盖原有的值
|
||
stored_psn = stored_psn + 1;
|
||
}
|
||
};
|
||
RegisterAction<psn_t, qp_reg_index_t, psn_t>(reg_rdma_sequence_number) set_psn = {
|
||
void apply(inout psn_t stored_psn, out psn_t output)
|
||
{
|
||
// 将 PSN 重新同步为 ACK 获取的值
|
||
stored_psn = eg_md.rdma_psn;
|
||
output = stored_psn;
|
||
}
|
||
};
|
||
|
||
action setEthernet()
|
||
{
|
||
hdr.ethernet.setValid();
|
||
hdr.ethernet.srcAddr = 0x08c0eb24686b; // Generator
|
||
hdr.ethernet.dstAddr = 0x08c0eb247b8b; // Collector
|
||
hdr.ethernet.etherType = ETHERTYPE_ROCE;
|
||
}
|
||
|
||
action setInfiniband_GRH()
|
||
{
|
||
hdr.grh.setValid();
|
||
hdr.grh.version = 6;
|
||
hdr.grh.class = 2;
|
||
hdr.grh.flow_lab = 0;
|
||
hdr.grh.pay_len = 44;
|
||
hdr.grh.next_hdr = 27;
|
||
hdr.grh.hop_lim = 1;
|
||
hdr.grh.src_gid = 0xfe800000000000000ac0ebfffe24686b;
|
||
hdr.grh.dst_gid = 0xfe800000000000000ac0ebfffe247b8b;
|
||
}
|
||
|
||
action setInfiniband_BTH()
|
||
{
|
||
hdr.bth.setValid();
|
||
hdr.bth.opcode = 0b00010100; // Default is RDMA Fetch&Add
|
||
hdr.bth.solicitedEvent = 0;
|
||
hdr.bth.migReq = 1;
|
||
hdr.bth.padCount = 0;
|
||
hdr.bth.transportHeaderVersion = 0;
|
||
hdr.bth.partitionKey = 0xffff;
|
||
hdr.bth.fRes = 0;
|
||
hdr.bth.bRes = 0;
|
||
hdr.bth.reserved1 = 0;
|
||
hdr.bth.destinationQP = eg_md.queue_pair; // 指定目的地队列对 (QP) 标识符
|
||
hdr.bth.ackRequest = 0;
|
||
hdr.bth.reserved2 = 0;
|
||
}
|
||
|
||
/* Fetch & Add RDMA operation */
|
||
action setInfiniband_AETH()
|
||
{
|
||
hdr.atomic_eth.setValid();
|
||
hdr.atomic_eth.virtualAddress = eg_md.memory_address_start + eg_md.memory_address_offset;
|
||
hdr.atomic_eth.rKey = eg_md.remote_key;
|
||
// Execute the increment operation
|
||
hdr.atomic_eth.data = 1;
|
||
}
|
||
|
||
apply{
|
||
setEthernet();
|
||
@stage(2)
|
||
{
|
||
// 如果为 TCP 或 UDP 数据包, 则转换为 RDMA 数据包
|
||
if(hdr.tcp.isValid() || hdr.udp.isValid()){
|
||
// GRH Header
|
||
setInfiniband_GRH();
|
||
// BTH Header
|
||
setInfiniband_BTH();
|
||
|
||
// 读取并更新该 RDMA 连接的 PSN
|
||
hdr.bth.packetSequenceNumber = get_psn.execute(eg_md.qp_reg_index);
|
||
|
||
// AETH Header
|
||
setInfiniband_AETH();
|
||
|
||
// iCRC Header
|
||
hdr.icrc.setValid();
|
||
}
|
||
}
|
||
|
||
// 使原始数据包的相关报头失效
|
||
hdr.ipv4.setInvalid();
|
||
if (hdr.tcp.isValid()){
|
||
hdr.tcp.setInvalid();
|
||
}
|
||
else if (hdr.udp.isValid()){
|
||
hdr.udp.setInvalid();
|
||
}
|
||
}
|
||
}
|
||
|
||
/* 出口控制块部分校对完毕, 没有问题 */
|
||
control SwitchEgress(inout headers hdr,
|
||
inout egress_metadata_t eg_md,
|
||
in egress_intrinsic_metadata_t eg_intr_md,
|
||
in egress_intrinsic_metadata_from_parser_t eg_intr_from_prsr,
|
||
inout egress_intrinsic_metadata_for_deparser_t eg_intr_md_for_dprsr,
|
||
inout egress_intrinsic_metadata_for_output_port_t eg_intr_md_for_oport)
|
||
{
|
||
|
||
ControlPrepareMemoryAddress() PrepareMemoryAddress;
|
||
ControlConvertToRDMA() ConvertToRDMA;
|
||
|
||
apply{
|
||
if(hdr.ipv4.srcAddr != 0xc0a80403 && hdr.ipv4.dstAddr != 0xc0a80403){
|
||
eg_md.srcIP = hdr.ipv4.srcAddr;
|
||
eg_md.dstIP = hdr.ipv4.dstAddr;
|
||
eg_md.proto = hdr.ipv4.protocol;
|
||
if(hdr.tcp.isValid()){
|
||
eg_md.srcPort = hdr.tcp.srcPort;
|
||
eg_md.dstPort = hdr.tcp.dstPort;
|
||
}
|
||
else if(hdr.udp.isValid()){
|
||
eg_md.srcPort = hdr.udp.srcPort;
|
||
eg_md.dstPort = hdr.udp.dstPort;
|
||
}
|
||
PrepareMemoryAddress.apply(hdr, eg_md, eg_intr_md);
|
||
ConvertToRDMA.apply(hdr, eg_md);
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
/* 出口逆解析器部分校对完毕, 没有问题 */
|
||
control SwitchEgressDeparser(packet_out pkt, inout headers hdr, in egress_metadata_t eg_md, in egress_intrinsic_metadata_for_deparser_t eg_dprsr_md)
|
||
{
|
||
Checksum() ipv4_checksum;
|
||
apply{
|
||
// Update IPv4 checksum
|
||
hdr.ipv4.hdrChecksum = ipv4_checksum.update(
|
||
{hdr.ipv4.version,
|
||
hdr.ipv4.ihl,
|
||
hdr.ipv4.dscp,
|
||
hdr.ipv4.ecn,
|
||
hdr.ipv4.totalLen,
|
||
hdr.ipv4.identification,
|
||
hdr.ipv4.flags,
|
||
hdr.ipv4.fragOffset,
|
||
hdr.ipv4.ttl,
|
||
hdr.ipv4.protocol,
|
||
hdr.ipv4.srcAddr,
|
||
hdr.ipv4.dstAddr});
|
||
|
||
pkt.emit(hdr.ethernet);
|
||
pkt.emit(hdr.ipv4);
|
||
pkt.emit(hdr.udp);
|
||
pkt.emit(hdr.tcp);
|
||
pkt.emit(hdr.grh);
|
||
pkt.emit(hdr.bth);
|
||
pkt.emit(hdr.atomic_eth);
|
||
pkt.emit(hdr.icrc);
|
||
}
|
||
}
|
||
|
||
|
||
Pipeline(SwitchIngressParser(),
|
||
SwitchIngress(),
|
||
SwitchIngressDeparser(),
|
||
SwitchEgressParser(),
|
||
SwitchEgress(),
|
||
SwitchEgressDeparser()
|
||
) pipe;
|
||
|
||
Switch(pipe) main;
|